1. Field of the Invention
The present invention generally relates to clock circuits for maintaining data integrity in a switching network, and more particularly, to an apparatus and method of preventing cell data loss during clock switching in a network system having redundant clocks in a redundant clock system.
2. Description of the Prior Art
Asynchronous Transfer Mode (ATM) networks require bit and cell timing. At any entrance point to an ATM multiplexer or ATM switch, an individual synchronizer is provided which adapts the cell timing of the incoming signal to the internal timing. Although the ATM network need not be synchronous, it must be able to accommodate Synchronous Transfer Mode (STM)-based applications, including audio and video transmission, as long as they continue in use. To this end the sampling clock of the sender must be provided to the receiver in order to avoid slips. This implies requirements on the network in terms of support for synchronization of the access lines and tolerable slips in the case of synchronization failure.
Redundant clock systems are utilized to ensure standby connections in the event of failure of the main clock. Existing conversion solutions, however, require complex hardware schemes with equally complex timing schemes to convert and transfer the requisite data.
In light of the foregoing, there exists a need for an apparatus and method of preventing cell data loss during clock switching in a network system having redundant clocks.